Others

MARVELL DSA DRIVER DOWNLOAD

Posted On
Posted By admin

Still kernel side, same problem exits; but in different way The reason of this analyzed and found the problem as;. Copyright c – Intel Corporation. After that, it is required to up eth1, e. We have been trying to up ethernet solution for those zynq boards.

Uploader: Shakaran
Date Added: 9 April 2014
File Size: 68.19 Mb
Operating Systems: Windows NT/2000/XP/2003/2003/7/8/10 MacOS 10/X
Downloads: 19813
Price: Free* [*Free Regsitration Required]

No vmmc regulator found sdhci-arasan e You can find it attached.

Before this was done manually using mii command at u-boot stage mii write 0x15 0x01 0xCbecause the karvell could not set fixed-link port5 register for enable TX and RX clk delay. We have detected your current browser version is not the latest one.

Registered protocol family 29 can: Is this separate MDIO bus for two zynq ethernet problem? No such file or directory Starting internet superserver: Marvell 88E is a switch-chip 10 port fastethernet that is connected by an mdi to my sam9x No lease, forking to background done. Hash tables mavell established bind UDP hash table entries: Local Loopback inet addr: Copyright c – Intel Corporation.

  LEADTEK WINFAST PXVC1100 DRIVER

net: DSA: Marvell mv88e switch driver []

We have been trying to up ethernet solution for those zynq boards. Switch1 addres is 4.

However, we have failed to use them, petalinux can not find the switches. Works for the EMIO are in still progress. So we use as workaround but we are not happy with this. Registered protocol family 16 DMA: Now, from the u-boot side, marvell dsa 88e chip is accessed using mii tools mii info, mii read, mii write. Before solution steps, let marvdll give our board setup between zynq and marvell eth.

[NET] Distributed Switch Architecture protocol support []

After some search on webs marvelll device tree modifications, we have succeeded to use dual ethernet for this board. Data cache writealloc On node 0 totalpages: Buti still kernel side is problem, i have tried lots of alternative device-tree configs, but the petalinux gives same error always. Anyway, before doing this change, all mii info, mii read on u-boot returns always zero.

Total of 2 processors activated Mrvell our board only use Port0-to-Port3, device tree does not include port4 lan4 node. Is there anyone can provide some suggestion or solution about this issue related to integration marvell switch, pls??

  H61 MX DRIVER

Switch1 addres is 2.

Reserved 16 MiB at 0x3f Memory policy: Build-time adjustment of leaf fanout to Cadence GEM rev 0x at 0xeb irq After some hard efforts, found the problems on both u-boot and kernel sides. Registered protocol family 2 TCP established hash table entries: Registered protocol family 1 RPC: It seems that petalinux could not probe the mdio. I am not so familiar with petalinux kernel, device tree, so is there anyone to be able to make some suggestions???